1. Technical Field
The present invention relates to a signal processing circuit, unit such as a scanner; digital copier, a digital multi-functional apparatus, and a facsimile machine equipped with the signal processing circuit, an image scanner, and an image forming apparatus mounting the image scanning unit.
2. Description of the Background Art
Scanners are used to scan images from documents or the like. Specifically, light reflected from a document face-bearing an image thereon (hereinafter, “document image” or “document”) is received by an image sensor such as a charge coupled device (CCD), and converted to electrical signals to obtain a scanned document image. In general, a scanner uses a plurality of operating modes, such as a scanning mode, a standby mode, and a reduced-power mode or energy saving mode.
The scanning mode denotes a state in which a scanning operation is conducted. The standby mode denotes a state in which a scanning operation is not conducted, but a power-ON condition is set for an apparatus, which means the apparatus as a whole is in normal operational condition. The reduced-power mode or energy saving mode denotes a state in which a power-OFF condition is set for the apparatus, in which only minimal power is supplied to the apparatus.
In actual use, the time that an apparatus is maintained in the standby mode is relatively longer than the time period of the scanning mode and/or reduced-power mode. Therefore, conventional image scanners continue to consume power during the standby mode unnecessarily, and overall power consumption is not reduced to the extent possible.
In view of such power consumption issue, a conventional control method sets apparatuses at the power-OFF condition during the standby mode similar to the reduced-power mode. Such a method can reduce power consumption during the standby mode. However, if the power-OFF condition is set for the standby mode, it is necessary to wait for register settings and circuit operation to stabilize when the power-ON condition is set again to return to the normal operating mode.
Further, because supply of clock signal and/or synchronization signal to one or more later-stage units is stopped during the standby mode (power-OFF), when the power-ON is resumed during the standby mode, it is necessary to wait for the operation of the later-stage units to stabilize when an instruction to return to the normal operating mode is received.
In view of such waiting time issue, JP-4064161-B discloses a configuration controlling the supply of signal that passes a phase-locked loop (PLL) circuit of a timing generator, in which signal supply from the PLL circuit can be set to ON or OFF. With such a configuration, the operating modes can be shifted without waiting for stabilization of the PLL circuit, enabling reduction of unnecessary power consumption and high speed shifting to the power supply mode.
However, because the method of JP-4064161-B stops the supply of clock signal and/or synchronization signal to later-stage units disposed after the timing generator, when an instruction to return to the normal operating mode is received during the standby mode, a long time is required to return to the normal operating mode.